1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a flash memory and manufacturing method thereof.
2. Description of the Related Art
Memory is a type of semiconductor device for holding information and storing digital data. As the microprocessor of a computer becomes more powerful, the size of software programs and the amount of computation that can be carried out increase exponentially. As a result, the demand for memory with very high storage capacity increases at an alarming rate. To fabricate memories with a large storage at a low production cost, techniques and processes that can increase the level of integration has been eager sought and has become the principle driving force behind the constant improvement in semiconductor devices.
For example, in an flash memory, data can be stored, read out or erased from the flash memory numerous times and any stored data is retained even after power is cut off. With these advantages, flash memories have become one of the principle non-volatile memories commonly used in personal computers and electronic equipment.
Typically, a flash memory device is designed with a stacked gate structure including a polysilicon floating gate and a polysilicon control gate. The floating gate is disposed between the control gate and the substrate and is disposed in a floating state without any connection with other circuits. The control gate is generally connected to a word line. In addition, the flash memory may include a tunneling oxide layer and an inter-gate dielectric layer disposed between the substrate and the floating gate and between the floating gate and the control gate respectively.
In general, the floating gate and the control gate of the stack gate flash memory are defined by performing photolithographic and etching processes. However, defining the floating gate and the control gate through the photolithographic and etching processes not only increases processing difficulties, but also leads to the so-called critical dimension limitation of the photolithographic process. Consequently, it is very difficult to reduce the line width of devices, thereby creating an immense barrier for increasing the level of integration of the devices.
On the other hand, with the trend toward for increasing the level of integration forces the miniaturization of devices according to design rules. In the operation of flash memory, the operating voltage can be lower if the gate-coupling ratio (GCR) between the floating gate and the control gate is larger. One of the methods for increasing the gate-coupling ratio (GCR) includes increasing the capacitance of the inter-gate dielectric layer or reducing the capacitance of the tunneling oxide layer. The principle method for increasing the capacitance of the inter-gate dielectric layer includes increasing the overlapping area between the control gate layer and the floating gate. Thus, the common goal for the manufacturers of memory devices is to find an optimal process capable of reducing device dimension and yet somehow able to increase the overlapping area between the control gate layer and the floating gate so that a high-quality and highly integrated memory package is produced.